Multiplexers are frequently used in control logic to perform a select or a decode function. This application is primarily concerned with 4-to-1 multiplexers. Such a multiplexer is illustrated schematically in FIG. 1. Multiplexer 100 receives four input signals, I1, I2, I3 and I4, are respective input terminals. Multiplexer 100 also receives two select signals, S0 and S1, at respective control terminals. Multiplexer 100 supplies an inverted version of one of the input signals I1 to I4 to its output terminal depending on the state of the two selection signals S0 and S1. Table 1 shows the truth table of multiplexer 100.
TABLE 1 ______________________________________ S0 S1 Output ______________________________________ 0 0 I1 0 1 I2 1 0 I3 1 1 I4 ______________________________________
FIG. 2 illustrates a prior art circuit embodying a multiplexer 110. This prior art multiplexer 110 implements a one-stage decode of the select lines via inverters 201 and 202, and NOR gates 221, 222, 223 and 224. Depending on the state of select signals S0 and S1 only one of NOR gates 221, 222, 223 and 224 is active. The active NOR gate 221, 222, 223 or 224 together with the corresponding inverter 231, 232, 233 or 234 enables one of the four transmission gates 211, 212, 213 or 214. The outputs of transmission gates 211, 212, 213 and 214 are connected in a wired OR fashion to the input of inverter 240. Because only one of transmission gates 211, 212, 213 and 214 is enabled at any time no actual logical OR function takes places in this wired OR input to inverter 240. Inverter 240 provides final inversion as well as output buffering. This circuit requires 38 transistors (note NOR gates 211, 222, 223 and 224 require 4 transistors each). This prior art multiplexer 110 minimizes delay from the data inputs to output at the expense of longer delay paths from the select inputs to data output. For the worst case path delay, inputs S0, S1, and any input I1, I2, I3 or I4 have to traverse six, six, and two (6/6/2) transistors to output, respectively.
FIG. 3 illustrates a modular design approach. The multiplexer 120 includes three 2-to-1 multiplexers. A first 2-to-1 multiplexer consists of transmission gates 211 and 212 and inverter 241. Transmission gates 211 and 212 are driven in the opposite phase from the select signal S0 and its inverse provided by inverter 201. A second 2-to-1 multiplexer consists of transmission gates 213 and 214 and inverter 242. The outputs of these two 2-to-1 multiplexers at inverters 241 and 242 are connected to the third 2-to-1 inverter consisting of transmission gates 215 and 216 and inverter 243. Inverter 240 provided at the output maintains the inverting attribute of multiplexer 120. The multiplexer 120 includes a total of 24 transistors, which represents a 58% reduction in transistor count relative to the prior art multiplexer 110 illustrated in FIG. 2. This area reduction is at the expense of a greater gate delay. The worst case path delay from inputs S0, S1, and any input I1, I2, I3 or I4 is six, four, and five (6/4/5), respectively.
A third prior art multiplexer 130 is illustrated in FIG. 4. Three redundant inverters 241, 242 and 243 of multiplexer 120 illustrated in FIG. 2 are eliminated. This leads to the structure called TG-TG-INV for transmission gate, transmission gate and inverter illustrated in FIG. 4. The TG-TG-INV multiplexer 130 illustrated in FIG. 4 requires 18 transistors. Compared to the prior art multiplexer 110, the TG-TG-INV multiplexer 130 uses a factor of 2.1 fewer transistors. The input to output path delay has been reduced from 6/6/2 of multiplexer 110 to 4/3/3. Both the multiplexer 120 formed of three 2-to-1 multiplexers and the TG-TG-INV multiplexer 130 utilize two-stage decode and therefore have a more balanced delay from each input to the output when compared to the prior art multiplexer 110.